Hi, This is Asif Hasan

- A passionate and detail-driven Design for Testability (DFT) Engineer with over 2 years of experience turning complex SoC challenges into high-performance, testable solutions.

Currently, I'm working as a DFT Engineer at Quest Global. My journey in semiconductor design has been fueled by curiosity, precision, and a relentless drive to innovate. I specialize in SCAN insertion, test compression, test pattern generation, and coverage analysis — all powered by hands-on mastery of industry-standard tools like Synopsys DFTMax, TestMax ATPG, and Cadence Xcelium.

From medical chips to encryption-enabled SoCs, I’ve worked across advanced technology nodes (6nm to 180nm), contributing to cutting-edge projects through both technical leadership and collaborative teamwork. I thrive in debugging simulations, optimizing test coverage, conversion of test vectors and developing custom automation scripts in TCL, Python, and Bash to elevate design efficiency.

My technical foundation is built on a Bachelor of Science in Electrical and Electronic Engineering from Ahsanullah University of Science & Technology, where I majored in Electronics & VLSI. This academic background fuels my analytical mindset and commitment to engineering excellence.

Beyond my professional work, I am actively engaged in academic research. My first conference paper, titled “Design of 4-Stage Single-Ended Ring Oscillators with Quadrature-Phase Output,” is being published by IEEE, marking the beginning of my journey into advanced circuit design. Currently, I am exploring the intersection of hardware security and cryptography, with a focus on developing safer and more resilient electronic systems.

My research broadly focuses on,