[Project name]
Write a description of your project in one or two sentences
HalfAscon is a lightweight authenticated encryption algorithm based on the ASCON cipher. It retains the security features of ASCON while reducing the block size to 64 bits, making it suitable for resource-constrained environments.
Features
64-bit block size
Authenticated encryption with associated data (AEAD)
Lightweight and efficient
Suitable for resource-constrained devices
Provides data integrity and confidentiality
This is a quick and simple AES Encryption implementation using Verilog Programming Language. The code takes in a 128 bit data and 128 bit Key from the user and encrypts it according to AES algorithms and standards.
It was my bachelor's thesis. I tried to make a whole CPU with the supervision of Mr. Jamal Uddin Ahmed.
Wrote Verilog code for 8-bit ALU, Register, and Control-Unit of the CPU. Also designed schematic and analog layout for 8-bit ALU & Register with clock speed of 1.82 MHz.
Performed synthesis and physical design for 8-bit ALU, Register, and Control-Unit with 3 different aspect ratios for minimum area.
Analysed the performance between analogue design and physical design in terms of power consumption, overhead.
Performed synthesis using Genus with required SDC constraints and generated netlist from Verilog code.
Performed physical design using Encounter with required design constraints.
Generated STA reports before CTS & after routing and cleared all violations.
Performed physical verifications (DRC, Geometry, Connectivity, ARC) and cleared all violations.
Tools Used: Cadence Genus, Cadence Encounter.
